Slave clock generation system and method for synchronous

Abstract

A slave clock generation system and method suitable for use with synchronous telecommunications networks generates one or more slave clocks from a selected reference clock using a direct digital synthesis technique. A multiplexer selects a reference clock from a number of available sources, each of which can be at its own spot frequency, based on a predetermined selection order. Toggle detectors monitor each of the available clock sources, and block the selection of any that are not within a specified frequency range. A local oscillator establishes short-term and long-term measurement periods; the cycles of the selected reference clock are counted over consecutive short-term measurement periods to determine the relative frequency of the selected clock with respect to the frequency of the local oscillator. The cycle counts are fed to a phase-to-clock converter, which produces a slave clock output having a frequency that varies with the relative frequency measured for the selected clock. Rounding errors are countered by monitoring both the generated slave clock and the selected reference clock over a long-term measurement period, with the difference between these two cycle counts used in a feedback path to correct the output frequency. The invention's mostly-digital implementation improves its noise-rejection and suppression characteristics, and enables the system to be integrated on a common substrate.