Low priority fifo request assignment for dram access

Abstract

The present invention is directed to a display FIFO module for use in DRAM interface that includes a DRAM controller sequencer which prioritizes requests for DRAM access received from various modules, such as a CPU, a BitBLT engine module, and a half frame buffer logic module, etc. The display FIFO module issues low and high priority requests for DRAM access to the DRAM controller sequencer for loading the FIFO with display data to be transferred to the display device. The low priority request and high priority request are both issued when the FIFO must receive new data or FIFO underrun will occur. If the FIFO data level rises above the low threshold value, the low priority request will be removed by the display FIFO module. The hysteresis effect exhibited by the low priority request prevents it from being immediately re-asserted as soon as the FIFO level falls to the low threshold and prevents oscillation of the FIFO level about the low threshold value. The low priority threshold value is variable and is calculated such that the hysteresis time is substantially equal to the time required to service at least one other device n from the DRAM. This ensures that devices other than the display will utilize all of the DRAM availability time when it is not being used by the display.