The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 12, 2000
Filed:
Sep. 05, 1997
Edmond H Barakat, Allentown, PA (US);
Anthony Botzas, Allentown, PA (US);
Lucent Technologies, Inc., Murray Hill, NJ (US);
Abstract
An apparatus and method employs a First In, First Out (FIFO) buffer to separate a first logic block operating at a first rate, such as 33.75 MHz, from a second logic block operating at a second rate, such as 27 MHz, which is lower than the first rate. The dual port FIFO operates with asynchronous Read and Write ports, and the Write port controls the input of data from the first logic block at the first rate to the FIFO. The FIFO provides a value indicating that the FIFO is full. Enablement of the Read port is based upon the presence of data in the FIFO and a synchronization signal for the data. Once enabled, the data is transferred from the FIFO to the second logic block at the second rate. A flag value of the FIFO is set when the FIFO buffer is full, and is used by the first logic block to interrupt data transfer into the FIFO at the first rate to allow data provided at the FIFO output at the second rate to empty the FIFO buffer.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile