The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 12, 2000
Filed:
Mar. 10, 1998
James D Allan, Colorado Springs, CO (US);
Iulian C Gradinariu, Colorado Springs, CO (US);
Cypress Semiconductor Corporation, San Jose, CA (US);
Abstract
A memory device includes a memory array having bit line pair interface connections being made alternatively at each side of the array. Column redundancy bit line pairs may be directed to either side of the array. In addition, bit line loads are placed at both ends of respective bit line pairs to improve speed. Stated differently, the memory device includes a bit line pair accessible from either of two sides of the memory array. The array may be one of a number of blocks within the memory device, while the bit line pair may comprise a redundant column bit line pair. The two sides of the memory array from which the bit line pair is accessible may be opposite sides of the array. In addition, the memory device may also include interdigitated bit line pairs within the memory array. One or more bit line pairs, including the above-mentioned redundant column bit line pair, may have bit line loads (e.g., transistors) at each end.