Integrated circuit memory device

Abstract

An integrated circuit memory device includes a memory cell block including a memory cell array which has a plurality of odd and even numbered subword lines extending therethrough. A first decoder is disposed at a top side of the memory cell block, which receives a first row address and generate a plurality of first control signals in response thereto. A second decoder is disposed at a bottom side of the memory cell block, which receives the first row address and generate a plurality of second control signals in response thereto. A row decoder receives a second row address and generates a word line signal in response thereto. A first driver block including a first plurality of subword line drive circuits adjacent to the memory cell array wherein each of the subword line drive circuits of the first plurality is connected to a respective odd numbered subword line of the memory cell array, and wherein the first plurality of subword line drive circuits drive the respective odd numbered subword lines responsive to odd numbered control signals of the first and the second control signals and the word line signal. A second driver block including a second plurality of subword line drive circuits adjacent to the memory cell array opposite to the first driver block wherein each of the subword line drive circuits of the second plurality is connected to a respective even numbered subword line of the memory cell array, and wherein the second plurality of subword line drive circuits drive the respective even numbered subword lines responsive to even numbered control signals of the first and the second control signals and the word line signal.