Semiconductor memory device in which a bit line pair having a high load

Abstract

When a minute electric potential difference on a bit line pair is transmitted to sense amplifier, a bit line pair having a high load is electrically separated from the sense amplifier, thereby performing amplification. Therefore, reading speed can be increased. Furthermore, a plurality of sense amplifier are provided corresponding to each bit line pair. While any of the sense amplifier amplifies the read data, data held in another sense amplifier are written to the memory cell through the corresponding bit line pair. Consequently, in the case where the writing and reading operations are carried out alternately, the delay of a reading operation start period can be reduced during the writing operation. Consequently, it is possible to implement a memory device capable of increasing reading speed and reducing the delay of the reading operation start period by the writing operation even if writing frequency is almost equal to reading frequency.