Semiconductor memory circuit with bit lines discharging means

Abstract

A semiconductor memory circuit reduces a current consumed by sense amplifiers, prevents erroneous operation, and can operate at high speed. The semiconductor memory circuit has a plurality of memory blocks each comprising a decoder, a plurality of memory cells, a plurality of sense amplifiers for amplifying potential changes in bit lines, a data latch for latching outputs from the sense amplifiers, a plurality of nMOS transistors for discharging the bit lines, an NAND gate for generating a sense amplifier de-energizing signal RD, and a reference voltage generator. In response to a memory block selecting signal CS, the NAND gate generates the sense amplifier de-energizing signal RD, which is applied to energize the nMOS transistors to discharge the bit lines of a memory block which is not selected.