The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 12, 2000
Filed:
Jun. 30, 1998
Susan K Radford, Fort Collin, CO (US);
Heather L Volesky, Fort Collin, CO (US);
Hewlett-Packard Company, Palo Alto, CA (US);
Abstract
Printed circuit board has first, second and third sets of connection points operable to connects to first, second and third integrated circuits. Each set of connection points is arranged in a grid pattern having a center pairs of orthogonal axes intersect. The grids define parallel planes. The pairs of orthogonal axes of the second grid are rotated counterclockwise relative to those of the first grid by at least 5 but not more than 25 degrees. Signal connection points in the first and second grids are concentrated in corners closet to the center of the third grid. Signal connection points in the third grid are concentrated in the half closest to the centers of the first and second grids. Alternatively, when signal connection points are concentrated elsewhere in the grid, the pairs of axes for the second grid are rotated relative to those of the first by an amount other than 0, 45, 90, 135, 180, 225, 270 and 315 degrees. First and second sets of mounting holes attach first and second heat dissipators. The second set of mounting holes is rotated relative to the first by either 0, 90, 180 or 270 degrees. First conductive traces connect signal connection points in the third grid to signal connection points in the grid. Second conductive traces connect the signal connection points in the grid to signal connection points in the second grid. The aggregate conductive paths, formed from die to die by the first and second sets of conductive traces and the corresponding conductors internal to the chip packages, all have the same length.