The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 12, 2000
Filed:
Nov. 04, 1998
Gerald L Esch, Jr, Ft. Collins, CO (US);
Agilent Technologies, Palo Alto, CA (US);
Abstract
The present invention is generally directed to a PVT compensated variable impedance output driver for driving a signal through a signal pad on a semiconductor device. In accordance with one aspect of the present invention, the output driver includes a plurality of p-channel field effect transistors (PFETs) electrically connected in parallel. A source node of each of the plurality of PFETs are electrically connected together, and a drain node of each of the plurality of PFETs are electrically connected together. The driver further includes a plurality of n-channel field effect transistors (NFETs) electrically connected in parallel. A source node of each of the plurality of NFETs are electrically connected together and a drain node of each of the plurality of NFETs are electrically connected together. Further, the drain nodes of the plurality of PFETs are electrically connected with the source nodes of each of the plurality of NFETs, and are further electrically coupled (preferably through an ESD resistor) to the signal pad. A first PFET of the plurality of PFETs has a gate node that is driven by an output of a pull-up predriver circuit and a first NFET of the plurality of NFETs has a gate node that is driven by an output of a pull-down predriver circuit. The remaining PFETs and NFETs, however, have gate nodes that are driven by signals from the pull-up and pull-down predeiver circuits, as controlled by calibration words generated by a control circuit. In accordance with yet another aspect of the present invention, a method is provided for controllably varying the output impedance of an output driver circuit that is configured to drive a signal through a signal pad on a semiconductor device.