The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 12, 2000
Filed:
Jul. 18, 1997
Reinhold Schoerner, Grossenseebach, DE;
Peter Friedrichs, Nuremberg, DE;
Siemens Aktiengesellschaft, Munich, DE;
Abstract
A method for producing a MIS structure on silicon carbide is provided. Given application of a known CVD method for occupying the surface of a SiC substrate provided with a gate oxide with the silicon serving as gate material, stationary positive charges arise in the region of the oxide/SiC boundary surface whose extremely high effective density (Q.sub.tot >10.sup.12 cm.sup.-2) disadvantageously influences the electrical properties of the finished component. The present method modifies the deposition conditions for the silicon serving as a gate material. Thus, the silicon is deposited from the vapor phase at a temperature of T<580.degree. C. and is thus amorphously applied. During the subsequent doping (drive-in of phosphorous at T>800.degree. C.), the amorphous silicon converts into the polycrystalline condition. Since the crystalline regions in the silicon layer can grow comparatively unimpeded and free of mechanical stresses, the effective density of the negative boundary surface charges arising in the gate oxide lies at values Q.sub.tot <10.sup.11 cm.sup.-2. The method is particularly applied in the manufacture of MOSFETs, MOS capacitors and the like.