The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 05, 2000
Filed:
Dec. 08, 1997
Bernhard H Andresen, Dallas, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A method and circuit for detecting a spurious lock signal from a lock detect circuit are disclosed. The method includes generating a lock signal (16, 58, 84) having two states: lock and unlock. The lock signal (16, 58, 84) is monitored at a debounce circuit (50, 80). A reference clock signal (56, 86) is then received at the debounce circuit (50, 80). A clean lock signal (68, 88) is generated by the debounce circuit (50, 80) when the lock state of the lock signal (16, 58, 84) is received for at least two cycles of the reference clock. If the lock state of the lock signal (16, 58, 84) is received for less than two cycles of the reference clock, a clean loss-of-lock signal (68, 88) is generated. The circuit for detecting a spurious lock signal (50, 80) includes a lock detect circuit for generating a lock signal (10) and a plurality of flip-flops (70, 72, 92, 94, 96, 98). Each flip-flop (70, 72, 92, 94, 96, 98) has a data input (54, 82), a clock input (60, 106), a clear input (62, 102) for receiving the lock signal, and a data output (66, 108). A reference clock signal (56, 86) is connected to the clock input (60, 106) of each flip-flop (70, 72, 92, 94, 96, 98). The circuit further includes a clear lock signal output (68, 88).