Phase locked loop for recovering clock

Abstract

A PLL (phase locked loop) for recovering a clock preventing a DC value of an output voltage of a phase detector from being deviated in one-sided direction and maintaining a center frequency of a VCO, to thereby minimize the occurrence of timing errors, in the case where the period of a reference input signal to the phase detector is irregular and a part of a pulse column of the signal is omitted, in performing a clock recovery operation in a digital magnetic recording equipment or a digital communication system. The PLL includes: a phase detector having first and second signal delay parts and a first logical computing element, for detecting a phase of an output signal; and a voltage controlled oscillator for generating a predetermined frequency signal, the phase is detector further comprised of a second logical computing element for logically operating a reference input signal and an output signal of the voltage controlled oscillator to thereby output the result signal, and a third logical computing element for logically operating the output signals from the first and second logical computing elements to thereby output the result signal.