Signal transfer devices having self-timed booster circuits therein

Abstract

Signal transfer devices enable multiple processors to act as drivers or receivers of signals which can transition from an invalid state to a valid state and then return to the invalid state in one clock cycle. The preferred signal transfer device includes a bus line, a plurality of bus drivers electrically connected to the bus line for initiating wired-OR signal transitions and at least one self-timed booster circuit electrically connected to the bus line. The self-timed booster circuit includes a first field effect transistor electrically connected in series between the bus line and a first reference potential and a second field effect transistor electrically connected in series between the bus line and a second reference potential. A timing circuit is also provided as a plurality of inverters which are electrically coupled in series. The timing circuit, which has an input electrically coupled to the bus line, performs a boolean inversion of the signals on the bus line after a first delay. A circuit is also provided for turning on the first and second field effect transistors during consecutive time intervals which are preferably nonoverlapping to thereby reduce power consumption. Here, the circuit may comprise a multi-input NOR gate having a first input electrically connected to the output of the timing circuit, a second input electrically connected to the bus line and an output electrically connected to a gate electrode of the first field effect transistor. This circuit may also comprise an inverter having an input electrically connected to the output of the timing circuit and an output electrically connected to a gate electrode of the second field effect transistor.