The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 05, 2000

Filed:

Mar. 02, 1998
Applicant:
Inventors:

Anilkumar Chinuprasad Bhatt, Johnson City, NY (US);

Donald Herman Glatzel, New Milford, PA (US);

Allen F Moring, Vestal, NY (US);

Voya Rista Markovich, Endwell, NY (US);

Kostas Papathomas, Endicott, NY (US);

David John Russell, Apalachin, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B32B / ;
U.S. Cl.
CPC ...
428209 ; 428210 ; 174255 ; 174257 ; 174262 ; 430 14 ;
Abstract

A circuit assembly that includes a circuitized substrate having a dielectric interior layer with a first surface and at least one hole therein. A filler material substantially fills the hole within the dielectric interior layer. A first wiring layer is positioned on the first surface of the dielectric interior layer, wherein the first wiring layer substantially covers the hole and assists in retaining the filler material within the hole in the dielectric interior layer. A first dielectric photoresist layer is positioned on the first wiring layer and on the first surface of the dielectric interior layer. The first dielectric photoresist layer also includes at least one hole therein. The filler material also substantially fills the hole within the first dielectric photoresist layer. A second wiring layer is positioned on the first dielectric photoresist layer and includes a plurality of conductive pads as part thereof. At least one external component can be electrically coupled to the conductive pads of the second wiring layer.


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