The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 05, 2000
Filed:
Nov. 06, 1996
Francois Silve, Lecannet, FR;
Arnold Ginetti, Antibos, FR;
VLSI Technology, Inc., San Jose, CA (US);
Abstract
A set of flat net descriptors are added to a hierarchical representation of a specified circuit design so as to provide a hierarchical view and a flat net view of the circuit design. The hierarchical representation includes a set of cell descriptors representing hierarchical cells in the specified circuit design, and a set of net descriptors representing portions of interconnections located within each hierarchical cell. Each net descriptor has associated therewith a list of endpoint descriptors representing endpoints of a corresponding one of the interconnections located within a respective hierarchical cell. The procedure for generating flat nets generates a flat net descriptor for each interconnection in the specified circuit. Each flat net descriptor has associated therewith a list of endpoint descriptors representing all endpoints of the interconnection. Each of the endpoint descriptor associated with a flat net descriptor represents an interconnection endpoint in a flat, top level circuit representation of the specified circuit design. A flat net pointer is added to each net descriptor in the hierarchical representation of the specified circuit design. The flat net pointer points to an associated one of the flat net descriptors. As a result, a flat net representation of any interconnection in the specified circuit design is accessible through the flat net pointer in each of the net descriptors representing the interconnection.