System for indicating status of a buffer based on a write address of the

Abstract

A buffer memory control device comprises a buffer memory which is divided into memory areas in cell units each consisting of plural pieces of data by addresses; a write address generation circuit for outputting a write address of the buffer memory; a read address generation circuit for outputting a read address of the buffer memory; a first register for decoding the write address, thereby outputting a flag signal indicating a write address before completion of writing data for each cell; a data decision circuit for deciding presence/absence of cell unit data in the buffer memory and performing read control of the buffer memory on the basis of the flag signal; a second register for decoding the read address, thereby indicating completion of reading data for each cell and outputting a flag reset signal for resetting the flag signal; and an overflow occurrence notification circuit for notifying a transfer source of overflow in the buffer memory on the basis of the flag signal, the data decision circuit performing read control of the buffer memory, and notifying a transfer source that transfer of write data should be aborted before the buffer memory overflows, and data being transferred for each cell, thereby avoiding loss of data.