Bit synchronizing circuit having high synchronization characteristics

Abstract

A bit synchronizing circuit is arranged by a bit synchronization counter constructed of an up/down counter or an adding/subtracting counter; an edge detector for detecting an edge of an input NRZ signal to output an edge detection pulse; two sets of edge number counters for counting total numbers of edge detection pulses outputted from the edge detector during a 1 cycle of the counting operation by the bit synchronization counter; and two sets of registers for fetching the count value of the bit synchronization counter at the time instant every time the edge detector outputs the edge detection pulse, and also for storing an accumulation value of the count values fetched during the 1 cycle of the counting operation by the bit synchronization counter. Both the two edge number counters and the two registers are operated with shifts of a half cycle, respectively. This bit synchronization circuit is further arranged by a judging circuit for judging a synchronization shift amount between the input NRZ signal and the counting operation by the bit synchronization counter based on the count values of the two edge number counters and the accumulate values stored in the two registers, and for outputting a correction signal corresponding to the judgment result to the bit synchronization counter.