Hybrid packet/cell switching, linking, and control system and

Abstract

The present invention is directed to a hybrid packet/cell switching, linking, and control system and methodology for sharing a common internal cell format that supports multiple protocol operations to support both high speed Ethernet and ATM. The architecture is a shared memory common internal cell architecture (ATM is the preferred embodiment), providing capabilities that support multicast data traffic (which is specific in a LAN environment) and accommodates a large shared buffer and linked list queue set groupings to control reading and retrieving the cell and packet encapsulated cell data types to permit intercoupling all combinations of cross/hybrid switching. The new hybrid switch provides both a full non-blocking packet (e.g., Ethernet) switch having a plurality of ports (e.g., 32 @ 100 Mbps (full or half duplex) ports) and a full non-blocking cell (e.g., ATM) switch having a plurality of ports (e.g., 32 @ 155 Mbps ports). In one embodiment, one or more ports can be used internally on the board for SAR functions. The hybrid switch supports a variety of interfacing speeds and types (e.g., from 10 Mbps Ethernet to 622 Mbps ATM ports, either directly or by additional multiplexing functions), while supporting mixed operation (i.e., ATM and Ethernet) in the same switch. The mixed operation is performed at the queue level. Supporting applications like LAN (Local Area Network) at the switch level especially benefit from the segmentation and reassembly feature being an intrinsic part of the switch design.