The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 29, 2000

Filed:

Sep. 30, 1999
Applicant:
Inventor:

Mamoru Fujita, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
36523006 ; 365233 ; 365236 ; 36523008 ; 36523003 ;
Abstract

The present invention provides a synchronous memory device having at least a multi-bit pre-fetch address generator circuit, and at least an access path which includes at least a command decoder having an output terminal connected to at least a follower circuit element which receives a command signal from the at least a command decoder, wherein the at least a multi-bit pre-fetch address generator circuit is connected to the at least a follower circuit element in parallel to the at least a command decoder, so that the at least a multi-bit pre-fetch address generator circuit is excluded from a transmission path of the command signal, whereby the at least a multi-bit pre-fetch address generator circuit generates a plurality of internal address signals independently from transmission of the command signal from the at least a command decoder to the at least a follower circuit element.


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