The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 29, 2000
Filed:
Mar. 06, 1998
Robert L Cloke, Santa Clara, CA (US);
David Price Turner, Los Gatos, CA (US);
Robert Ellis Caddy, Jr, Oronoco, MN (US);
Michael Rodger Spaur, Laguna Niguel, CA (US);
Western Digital Corporation, Irvine, CA (US);
Abstract
A disk drive comprising a plurality of read/write transducers, a programmable preamplifier, and a controller for furnishing control and data signals to the programmable preamplifier and for receiving data signals therefrom, is disclosed. The programmable preamplifier comprising a write data input circuit for receiving data signals to be supplied to a transducer, a read data output circuit for manifesting data signals supplied to said preamplifier unit by a transducer, and a transducer interface circuit for providing write data signals to a transducer and receiving read data signals from a transducer. The programmable preamplifier further comprises a multiplexer comprising a first multiplexer input connected to receive a first internal digital signal, a second multiplexer input connected to receive a second internal digital signal, a control input connected to receive a control signal for selecting between the first and second internal digital signals, and a multiplexer output for outputting the selected first or second internal digital signal. The multiplexer output is connected to an output terminal of the programmable preamplifier. The programmable preamplifier comprises a serial interface circuit for receiving serially presented control signals from the associated controller, including the control signal for selecting between the first and second internal digital signals.