The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 29, 2000

Filed:

Apr. 01, 1998
Applicant:
Inventors:

Dong-Gyu Kim, Kyungki-do, KR;

Kyung-Seop Kim, Kyungki-do, KR;

Woon-Yong Park, Kyungki-do, KR;

Byoung-Sun Na, Kyungki-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G02F / ; G02F / ;
U.S. Cl.
CPC ...
349 54 ; 349 40 ; 349192 ;
Abstract

Flat panel display devices having improved signal line repair capability utilize repair lines which have reduced parasitic capacitance with other active signal lines when connected to provide a repair function. This reduced parasitic capacitance is a result of a reduced number of overlaps between active signal lines (or other repair lines) and each repair line performing a repair function. A main repair line is provided on a display substrate to provide a repair function in the event one of the signal lines is defective. If a repair function is needed because a data line is defective (e.g., 'opened'), this main repair line is electrically connected to a first end of the defective data line and indirectly electrically connected to a second end of the defective data line. The indirect electrical connection is provided by a sub-repair line, which can be electrically connected (i.e., 'shorted') to the main repair line, and a data line extension which is electrically connected to a second end of the defective data line and the sub-repair line. To further reduce parasitic capacitance caused by overlaps between wiring patterns, the main repair line and data line extension are provided at a first wiring level and the data line and sub-repair line are provided at a second wiring level.


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