Timing circuit that selectively triggers on a rising or falling input

Abstract

A timing circuit can be selectively configured to generate output pulses in response to either the falling edges or the rising edges of an input signal. The timing circuit includes a multiplexer, an output pulse width controller (OPWC), a gating circuit (GC) and a latch circuit. The OPWC includes a delay circuit that can be configured to provide a predetermined delay .delta. that can be larger than the pulse width of the input signal pulses. The multiplexer is connected to receive a first input signal and an inverted version of a second input signal. The first input signal is used in a rising edge triggered mode, whereas the second input signal is used in a falling edge triggered mode. The multiplexer receives a mode signal to selectively output one of the input signals to the GC. The GC is also connected to receive the output signal from the OPWC. The OPWC is configured in conjunction with the selected signal from the multiplexer, to cause the GC and the latch circuit to generate output pulses having a predetermined pulse width equal to .delta., triggered by the rising edges of the selected signal. Because the second input signal is inverted, during the second mode the output pulses are in effect triggered by the falling edges of the second input signal.