Circuit for generating interleaved ramped voltage signals having

Abstract

A circuit having multiple channels for generating multiple ramped voltage signals (preferably of a type useful in an interleaved PWM dc/dc converter) such that each ramped voltage signal has a different phase, and all the ramped voltage signals have a uniform controlled maximum amplitude. The circuit can be implemented as an integrated circuit (or portion of an integrated circuit) which generates the multiple ramped voltage signals with uniform maximum amplitude in a manner independent of process and temperature variations in implementing and operating such integrated circuit. In preferred embodiments, the circuit includes a single amplifier having an input coupled to receive a reference signal (indicative of a preselected maximum ramped voltage amplitude) and an output which is coupled (in time-division-multiplexed fashion) to each of the ramped voltage generation channels, thus implementing time-division-multiplexed negative feedback loops which control the maximum amplitude of the ramped voltage signal generated by each channel. The input offset voltage error of the amplifier is applied across all channels equally. Preferably, the ramped voltage signal generating circuit also includes circuitry for generating clock signals for controlling generation of the ramped voltage signals. Another aspect of the invention is a method for generating multiple ramped voltage signals (preferably those of a type useful in an interleaved PWM dc/dc converter) such that each ramped signal has a different phase and a uniform, controlled maximum amplitude.