The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 29, 2000

Filed:

Jun. 24, 1998
Applicant:
Inventors:

Daniel M Kuchta, Cortlandt Manor, NY (US);

Jungwook Yang, West Nyack, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ; H03K / ; H03K / ;
U.S. Cl.
CPC ...
326 68 ; 326 83 ; 326116 ; 326121 ;
Abstract

A circuit for interfacing CMOS logic devices, having an output level range associated therewith, with MESFET logic devices, having an input level range associated therewith, comprises a depletion mode MESFET device, coupled between at least one CMOS device and at least one other MESFET device, the depletion mode MESFET device limiting a current through a gate-source junction thereof such that the output level range of the at least one CMOS device is altered to be compatible with the input level range of the at least one other MESFET device. Another circuit for interfacing CMOS logic devices, having an output level range associated therewith, with MESFET logic devices, having an input level range associated therewith, comprises: a source follower MESFET device coupled to an output terminal of at least one CMOS device; a first depletion mode MESFET device, coupled to the source follower MESFET device, the first depletion mode MESFET device limiting a current through a gate-source juction thereof such that the output level range of the at least one CMOS device is altered to be compatible with the input level range of at least one other MESFET device; and a second depletion mode MESFET device, coupled to the first depletion mode MESFET device, for providing a discharge path; wherein an input terminal of the at least one other MESFET device is coupled between the first and second depletion mode MESFET devices.


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