The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 29, 2000
Filed:
Jul. 21, 1998
Applicant:
Inventor:
Shingo Hanatani, Tokyo, JP;
Assignee:
Kabushiki Kaisha Toshiba, Kawasakishi, JP;
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ; H03K / ; H03K / ;
U.S. Cl.
CPC ...
326 39 ; 326 44 ; 326 45 ;
Abstract
There is provided a programmable logic array in which a precharge circuit is provided separately from precharge transistors. The precharge circuit can connect the one of wirings connecting memory cell transistors out of the memory cell transistor group constituting an AND plane to a power supply voltage at a same timing as that of the precharge transistors. Accordingly, the programmable logic array having the AND plane which can prevent variation of an output by improving charge share tolerance can be provided.
Hanatani, Shingo. (2000). Programmable logic array (U.S. Patent No. 6111428). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6111428
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