The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 22, 2000
Filed:
Sep. 13, 1996
Thomas Jefferson Runaldue, San Jose, CA (US);
Jayant Kadambi, Milpitas, CA (US);
Advanced Micro Devices. Inc., Sunnyvale, CA (US);
Abstract
The present invention comprises a system and method for reducing the pin count between a plurality of MAC and PHY devices within a switching element. In this embodiment, the switching element includes a plurality of general serial interfaces for providing connections between respective MAC and PHY devices and each of the plurality of general serial interfaces operates at a first data rate. The system and method comprises a multiplexer coupled to the plurality of general serial interfaces and a pad member including a plurality of pins. The pad member is coupled to the multiplexer and receives multiplexed signals from the plurality of general serial interfaces. The multiplexer operates at a second data rate that is a multiple of the first data rate. Generally, a system and method in accordance with the present invention allows for the multiplexing of a general purpose serial interface (GPSI) to reduce the pin count in some cases by as much as 75% and also synchronize the MAC/PHY interface. In this example, the multiplexer interface uses a total of 7 pins and supports a total of four MAC/PHY connections. If only GPSIs were utilized, 28 pins would be required for this function. The same multiplexing technique will also reduce the MAC/PHY interface in four 100 Mbps connections from 56 pins for a four port system to 18 pins. In each example the multiplexer interface will operate at four times the speed of the general serial interface.