Sense amplifier for high-speed integrated circuit memory device

Abstract

A sense amplifier can be used with a high-speed IC memory device, which sense amplifier can help reduce the sensing latency during read operations to the memory device so as to allow fast access speed to the memory device. The sense amplifier includes a first-stage circuit, coupled to the bit lines of the memory device, for amplifying the differential data signal on the bit lines. Furthermore, a second-stage circuit has an input side coupled to receive the output signal from the first-stage circuit and an output side coupled to the bit lines, and is used for amplifying the output signal from the first-stage circuit and feeding the amplified signal back to the bit lines. The first-stage circuit and the second-stage circuit in combination constitute a positive feedback amplification loop coupled to the bit lines for amplifying the differential data signal on the bit lines to a detectable level. This positive feedback amplification loop allows the differential data signal on the bit lines to be quickly amplified to the detectable level with a reduced sensing latency, thus increasing the access speed to the associated memory device. Moreover, even though the bit lines are increased in length, the sensing speed is not significantly affected. This feature can also help save circuit layout space.