Integrated circuit memory devices having self-test circuits therein and

Abstract

Integrated circuit memory devices having self test circuits therein may be tested by performing an interleave test on a plurality of memory banks in the memory device, to determine a first test failure and then performing a bank-by-bank test on the plurality of memory banks with all of a plurality of AC parameters set to respective minimum margin conditions, to determine a second test failure. These AC parameters may include a first bank active to first bank active time interval (tRC), a first bank active to first bank read time interval (tRCD), a first bank active to first bank precharge time interval (tRAS), a first bank precharge to first bank active time interval (tRP) and a column address to column address delay time interval (tCCD). A bank-by-bank test is then performed on the plurality of memory banks with all of the plurality of AC parameters set to respective maximum margin conditions, to determine a third test failure. Finally, a bank-by-bank test is performed on the plurality of memory banks with only one of the plurality of AC parameters set to a respective minimum margin condition. This latter step is repeated for each AC parameter and need not be performed unless the first and second test failures occur and the third test failure does not occur.