The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 22, 2000
Filed:
Apr. 06, 1999
John J Price, Jr, Edina, MN (US);
VTC Inc., Bloominton, MN (US);
Abstract
The present invention is a dual-input-to-single-output amplifier circuit having a processing amplifier, first and second coupling regions, first and second input impedance circuits, first and second feedback impedance circuits, first and second shunting impedance circuits. The processing amplifier has first and second input regions and an output region. The first and the second input regions each exhibit a relatively high circuit impedance. The output region exhibits a relatively low circuit impedance. The processing amplifier is capable of providing at the output region a signal in a first magnitude direction substantially similar to a signal provided at the second input region in the first magnitude direction but of a greater magnitude in the first magnitude direction. The processing amplifier is further capable of providing at the output region a signal in a second magnitude direction substantially similar to a signal provided at the first input region in the first magnitude direction but of a greater magnitude in the second magnitude direction. The first input impedance circuit is coupled between the first coupling regions and the first input region. The second input impedance is coupled between the second coupling region and the second input region. The first feedback impedance circuit is coupled between the output region and the first input region. The second feedback impedance circuit is coupled between the output region and the second coupling region. The first shunting impedance circuit is coupled between the first coupling region and a reference voltage terminal region. The second shunting impedance circuit is coupled between the second input region and the reference voltage terminal region.