The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 22, 2000
Filed:
May. 28, 1999
Applicant:
Inventor:
Hideki Taniguchi, Tokyo, JP;
Assignee:
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
326 81 ; 326 58 ; 326 63 ; 326 83 ;
Abstract
An input/output circuit in which, one of the two output signals from a signal level converting circuit is inputted into one input terminal of a NAND gate and into one input terminal of a NOR gate, while the other signal is inputted into the other input terminal of the NOR gate and also to the other input terminal of the NAND gate through an inverter. An output signal from the NAND gate and NOR gate is inputted into the gate of a PMOS transistor and into a gate of a NMOS transistor, which makes it possible to prevent the PMOS transistor and NMOS transistor from concurrently being ON and also prevents a through current from flowing therethrough.