The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 22, 2000
Filed:
Feb. 08, 1999
Steven H Kelem, Los Altos Hills, CA (US);
Gary R Lawman, San Jose, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
A programmable logic device (PLD) includes a plurality of logic resources, a plurality of multi-bit configuration memories (MBCMs), and a trigger logic structure. The plurality of MBCMs include multiple memory slices that allow the PLD to switch rapidly between configurations, or contexts. In one embodiment, at least one memory slice configures the PLD into a logic analysis context for providing on-chip testing. In one embodiment, the plurality of logic resources include a plurality of storage elements. State data generated by a user-defined context is stored in the plurality of storage elements. When the trigger logic structure provides a trigger signal, the PLD is reconfigured into the logic analysis context. The logic analysis context reads and processes the state data stored in the plurality of storage elements to test the performance of the user-defined context. In one embodiment, the storage elements are multi-bit micro-registers that store state data generated by a plurality of contexts implemented in the multiple-context PLD.