Non-volatile semiconductor memory device

Abstract

In a NAND EEPROM using the local self-boosting system, an intermediate voltage which allows a memory cell adjacent to a selected memory cell to be turned on is applied to the control gate of the adjacent memory cell. As a result, even if the adjacent memory cell is in a normally-off state, the potential of a bit line can be transmitted to the adjacent memory cell. Thus, the reliability of the write inhibition in a non-selected NAND memory cell column is improved, while data can be written at random into a plurality of memory cells in a selected NAND memory cell column. When data is to be erased, an absolute value of an erasing voltage applied to a control gate can be less. As a result, data can be erased by a lower erasure voltage than that required in the conventional art. Consequently, the element refinement, the reliability and the yield can be further improved.