The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 22, 2000

Filed:

Apr. 28, 1998
Applicant:
Inventors:

Warren D Grobman, Austin, TX (US);

Mark H Nodine, Austin, TX (US);

Assignee:

Motorola Inc., Schaumburg, IL (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
716-5 ; 703 14 ; 703 15 ;
Abstract

Very high speed circuits are adversely effected by parasitic capacitances and line resistances. At high speeds these values of capacitance and resistance change with frequency. A method of verification of the design of high speed circuits includes a simulation of the effects of these changes in resistance and capacitance which occur at high frequency. There is a logic component and a physical-layout component which are combined to provide a full simulation of the circuit taking into account these effects which occur at very high frequency. The physical-layout component utilizes Maxwell's equations in their entirety without removing the time dependent effects. One embodiment considers only cases defined by the bus protocol, reducing the computational penalty of complete electromagnetic simulation.


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