High speed, scalable microcode based instruction decoder for processors

Abstract

A microcode based decoder circuit for microprocessors that uses fast access tables to decode instructions. The pointers to the tables are generated directly from the instruction prefetch buffers. Information bits about the instruction are added to the tables at no extra cost and enable the faster decode of the instruction. The present invention includes the decode of an instruction using an entry ROM, which contains information regarding the instruction that can directly be used in generating the decoder outputs. This information is also used in selecting the correct ROM entry, thus enhancing the flexibility of the decoder, and to dynamically generate a generic microcode entry. Thus, microcode space requirements are reduced. A generic microcode instruction is used for commonly used, similar macroinstructions. This avoids duplication of microcode instructions and thus reduces the required microcode space. The invention also includes the generation of a generic microinstruction dynamically by using the predecoded information selected from the entry microcode table. This makes the generic microinstruction flexible and hence, it can be efficiently be used for many instructions. An entry microcode table, used for the efficient decode of an instruction, contains predecoded information about the instruction apart from the regular microinstruction, which is used directly to generate the decoder outputs and to select the correct microcode entry, and also for the generation of the generic microcode entry. The invention also includes accessing the entry ROM and the .mu.ROM in parallel, using the same address which is generated from the opcode and ModR/M bytes, and selecting one of their outputs. Thus the two ROMs are used efficiently in that the required time and logic are reduced.