The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 15, 2000
Filed:
Apr. 04, 1997
Jeffrey L Kerr, Garland, TX (US);
John Ling So, Plano, TX (US);
Steven R Magee, Carrollton, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
An integrated circuit (1720) includes a dual-port memory (3330.1) having a first memory port (Port A) and a second memory port (Port B), a bus interface block (5010) including bus master (5016) and bus slave circuitry (5018), and a byte-channeling block (5310) coupled between the first memory port (Port A) and the bus interface block (5010) operable to convert non-aligned data addresses into aligned data. Advantageously, this invention includes a single bus master serving all application hardware. This relieves the host of the extra burden of communicating to slave circuits, reducing host I/O MIPS significantly. The digital signal processor with an ASIC wrapper of this invention together provide super-bus-mastering to access the entire memory space in the system, including the entire virtual memory space accessible by the host processor. Other processes, systems, devices and methods are also disclosed.