Memory array with a simultaneous read or simultaneous write ports

Abstract

The simultaneous read or simultaneous write memory array of the present invention includes a core array of memory units, control logic, a first port I/O, a first port shift register, first port word line generation logic, a second port I/O, a second port shift register, and a second port word line generation logic. The memory unit includes a pair of cells formed from two inverters as well as read and write transistors. The pair of memory cells preferably use the same bit lines for being read or written. Still more particularly, the novel design of the memory units combines the read and write bit lines into a single bit line such that there is a first, single bit line for reading from a first cell in the memory unit and writing to a second cell in the memory unit; and there is a second, single bit line for reading from the second cell in the memory unit and writing to the first cell in the memory unit. This is advantageous because it reduces the number of bit lines needed for each cell and thereby reduces the overall area of the core array, reduces power dissipation, and reduces noise and cross talk.