The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 15, 2000
Filed:
Nov. 05, 1997
Yasukazu Kai, Miyazaki, JP;
Oki Electric Industry Co., Ltd., Tokyo, JP;
Abstract
The present invention relates to a semiconductor memory device having a memory cell array of a split-operation mode. The semiconductor memory device comprises a semiconductor chip having first through fourth sides, a first interconnection disposed along the first side of the semiconductor chip and supplied with a source potential level or a ground potential level, a second interconnection disposed along the second side opposed to the first side and supplied with the source potential level or the ground potential level, and a plurality of sub-array regions disposed between the first interconnection and the second interconnection. A plurality of memory cells and a plurality of sense amplifiers respectively connected to the memory cells are disposed in each of the sub-array regions. The memory cells and the sense amplifiers disposed in one of the sub-array regions are activated in response to the potential level supplied to the first interconnection. The memory cells and the sense amplifiers disposed in another one of the sub-array regions are activated substantially simultaneously with the memory cells and the sense amplifiers disposed in the above one of the sub-array regions in response to the potential level supplied to the second interconnection.