The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 15, 2000
Filed:
May. 24, 1999
Tae-Young Ha, Seoul, KR;
Abstract
A power amplifier for a radio communication system is provided which includes a divider for equally dividing a received signal into two signals, an amplifier for separately amplifying the divided signals with a same gain, and a combiner for combining the separately amplified signals into one output signal. The divider includes a first FET for equally dividing a signal received at a gate thereof into a signal being output at a drain thereof and a signal being output at a source thereof, a first inductor for coupling the drain of the first FET to a ground, a second inductor for coupling the source of the first FET to the ground, a first capacitor for coupling the drain of the first FET to an input of the first amplifier, and a second capacitor for coupling the source of the first FET to an input of the second amplifier. The amplifier includes at least one first amplifier for amplifying a signal output from the first capacitor, and at least one second amplifier for amplifying a signal output from the second capacitor. The combiner includes a second FET for combining a signal received at a drain thereof from the first amplifier and a signal received at a source thereof from the second amplifier, and outputting the combined signal at a gate thereof, a third inductor for coupling the drain of the second FET to the ground, a fourth inductor for coupling a source of the second FET to the ground, a third capacitor for coupling the drain of the second FET to an output of the first amplifier, and a fourth capacitor for coupling the source of the second FET to an output of the second amplifier.