The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 15, 2000

Filed:

Apr. 13, 1999
Applicant:
Inventors:

Neil Deustcher, Tempe, AZ (US);

Jack Wong, Phoenix, AZ (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
438261 ; 438265 ; 438258 ;
Abstract

A merged two-transistor memory cell of an EEPROM, and method of fabricating the cell, are provided. The memory cell includes a substrate and gate oxide layer formed on the substrate. It also includes a memory transistor having a floating gate and a control gate, and a select transistor having a gate that is shared with the memory transistor. The memory cell is configured so that the shared gate serves both as the control gate of the memory transistor and the wordline of the select transistor. The memory cell further includes a dielectric layer that is disposed between the floating gate and the shared gate. The dielectric layer is defined by an ONO film and a stacked oxide layer. In fabricating the memory cell, the ONO stack film is formed adjacent to the top surface of the floating gate and the stacked oxide layer is formed adjacent to the side surface of the floating gate.


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