The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 15, 2000

Filed:

Jul. 22, 1998
Applicant:
Inventors:

Dirk Tobben, Fishkill, NY (US);

Gill Yong Lee, Fishkill, NY (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G03F / ;
U.S. Cl.
CPC ...
430317 ; 430316 ; 430314 ;
Abstract

A method of forming a patterned conductive multilayer arrangement on a semiconductor substrate is provided which prevents photoresist poisoning by reactive nitrogenous substances from a silicon oxynitride layer forming a dielectric antireflective coating (DARC) for an overlying photoresist layer. The substrate has a first level conductive layer, e.g., of a metal, disposed in a region thereon, and is coated in turn with a dielectric insulation layer, e.g., of silicon dioxide, which overlies the first level conductive layer region, a dielectric antireflective coating (DARC) silicon oxynitride layer, an essentially reactive nitrogenous substance-free dielectric spacer layer, e.g., of spin-on glass (SOG), and a photoresist layer. The dielectric spacer layer prevents reactive nitrogenous substance transport therethrough from the DARC silicon oxynitride layer to the photoresist layer, thereby preventing poisoning of the photoresist layer. The photoresist layer is exposed and developed to uncover pattern portions of the dielectric spacer layer. The uncovered portions of the dielectric spacer layer and corresponding portions of the DARC silicon oxynitride layer are removed together, and then corresponding portions of the insulation layer, e.g., by a pair of tandem etching steps, to expose portions of the first level conductive layer for subsequent metallization.


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