Parallel backplane physical layer interface with scalable data bandwidth

Abstract

An interface between a parallel backplane bus of a physical layer of a communication device and a higher layer of the device is provided in a manner compatible with a serial bus architecture such as IEEE 1394. The interface includes a parallel backplane physical layer controller having multiple receive data lines for receiving data from the backplane bus, and multiple transmit data lines for transmitting data to the backplane bus. A link layer controller is coupled to the parallel backplane physical layer controller, and communicates with the parallel backplane physical layer controller over a data bus. The parallel backplane physical layer controller can provide an effective data bandwidth which is greater than its operating clock rate. The parallel backplane physical layer controller may also be operative to support communications with the backplane bus using a plurality of different backplane bus widths, such as a single data bit bus width, a two data bit bus width, a four data bit bus width and an eight data bit bus width. The throughput data bandwidth of the interface can therefore be scaled by selecting one of the data bus widths supported by the parallel backplane physical layer controller.