Device for organizing the access to a memory bus

Abstract

This invention relates to a device for organizing access to a bus connecting a memory to at least two entities issuing asynchronous binary signals representing requests for access to the bus. The device supplies binary signals to authorize the access to an entity based on a priority determination between the different requests and includes a priority decoder in wired logic associated with an input register. A loading of the state of the access request signals happens, if an access request is present while a read or write cycle of the memory is executed, upon the arrival of a pulse on a signal issued by a memory controller associated with the memory and indicative of the end of a memory cycle.