The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 08, 2000
Filed:
Feb. 06, 1998
Gregory Edward Beers, Austin, TX (US);
Richard Francis Frankeny, Cedar Park, TX (US);
Mithkal Moh'd Smadi, Round Rock, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method and circuit, for use with a parallel data bus of defined width, which provide a parallel data transmission and reception rate which is greater than the defined width of the parallel data bus. With respect to improving transmission, provided is a width-reduction circuit element, having at least two inputs through which are received a first set of parallel digital data signals and having one or more outputs through which are transmitted a second set of parallel digital data signals where the second set is both smaller than the first set and representative of the information contained within the first set. The one or more outputs interface with a parallel connector which is sufficient to form an operable connection with the parallel data bus of defined width. With respect to improving reception, provided is a width-expansion circuit element having one or more inputs through which are received a second set of parallel digital data signals and having at least two outputs through which are transmitted a first set of parallel digital data signals where the first set is both larger than the second set and representative of information encoded within the second set. The one or more inputs interface with a parallel connector sufficient to form an operable connection with the parallel data bus of defined width.