Synchronous semiconductor memory device employing temporary data output

Abstract

In a synchronous semiconductor memory device in which an internal clock signal from an internal timing clock signal generating circuit is branched in the form of a tree by driver circuits and applied to output buffers and data are output in synchronization with the internal clock signal, the driver circuit of the first stage is constituted by an NAND gate and an inverter. When output is to be temporarily stopped, an enabling signal is set to 'L' level, so that the NAND gate is closed, output of the clock signal to each driver circuit is stopped, and thus power consumption is reduced.