The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 08, 2000
Filed:
Apr. 27, 1999
Greg A Duba, Stonington, CT (US);
Edgar S Thaxton, Bradford, RI (US);
John Walter, Niantic, CT (US);
Other;
Abstract
In the particular embodiments described, an unlimited voltage static power converter includes an array of multi-level phase drivers consisting of a plurality of H-bridge power modules connected in series. The midpoint node of the series-connected power semiconductors is connected to corresponding midpoint nodes in adjacent H-bridges to achieve a desired high output voltage using available power switch ratings. A three-dimensional multi-level, multi-phase, multi-circuit array of H-bridges permits the use of the static power converter for high power applications, while providing a high degree of power quality. The power semiconductor switches are operated in accordance with a two-dimensional interleaved pulse width modulation algorithm which produces a waveform with a switching frequency that can be more than an order of magnitude higher than the switching frequency of a single power switch. PWM complementary triangle carrier waves are used for individual PWM control of each H-bridge in each multi-level phase driver, resulting in a two-dimensional interleaved control algorithm. Injection of harmonic or non-harmonic content into the PWM reference waveform further reduces harmonic and non-harmonic content of the output voltage waveforms. Part-load efficiency is increased using unique load partitioning methods, five of which are described herein.