Segmented dual delay-locked loop for precise variable-phase clock

Abstract

A segmented dual delay-locked-loop (DLL) has a coarse DLL and a fine DLL. Each DLL has a series of buffers, a phase detector, charge pump, and bias-voltage generator. The bias voltage controls the delay through the buffers. The bias voltage of the coarse DLL is adjusted by the phase comparator to lock the total delay through the buffers to be equal the input-clock period. The coarse DLL divides an input clock into M equal intervals of the input-clock period and generates M intermediate clocks having M different phases. An intermediate mux selects one of the M intermediate clocks in response to a phase-selecting address. The selected intermediate clock K and a next-following intermediate clock K+1 are both selected and applied to the fine DLL. The K clock is input to a series of N buffers in the fine DLL while the K+1 clock is directly input to a phase detector. The phase detector compares the K+1 clock to the K clock after the delay through the buffers. The bias voltage of the fine DLL is adjusted by the phase comparator to lock the total delay through the N buffers to the coarse interval between the K and K+1 intermediate clocks. Thus the input clock is divided into M intervals by the coarse DLL, then the fine DLL further divides one coarse interval into N intervals. Very fine phases are generated with only a M-buffer DLL and an N-buffer DLL.