The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 08, 2000
Filed:
Dec. 21, 1998
Mehrdad Nayebi, Palo Alto, CA (US);
Stephen D Edwards, San Jose, CA (US);
Phil Shapiro, Palo Alto, CA (US);
Sony Corporation of Japan, Tokyo, JP;
Sony Electronics, Inc., Park Ridge, NJ (US);
Abstract
A buffer circuit having a high input impedance. The buffer circuit comprises an input lead, a first stage having a first emitter follower transistor and a first level shifter transistor, a second stage having a second emitter follower transistor and a second level shifter transistor, and an output lead coupled to said second stage. The first emitter follower transistor is coupled to the input lead and coupled to the first level shifter transistor. The first and second stage of the buffer circuit acts as a voltage follower. The second emitter follower transistor is coupled to the second level shifter transistor, while the second emitter follower transistor is coupled to the first emitter follower transistor. The buffer circuit has a high input impedance and very low leakage current. Hence, it is ideal for sampling filter components of a phase lock loop circuit within a high frequency clock generation circuit thereby reducing clock jitter.