The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 08, 2000
Filed:
Jul. 14, 1998
Chih-Hsien Wang, Hsinchu, TW;
Min-Liang Chen, Hsinchu, TW;
Mosel Vitelic, Inc., Hsinchu, TW;
Abstract
A method of forming an integrated circuit device, and in particular a CMOS integrated circuit device, having an improved lightly doped drain region. The methods include the steps of providing a semiconductor substrate with a P type well region and an N type well region. Gate electrodes are formed overlying gate dielectric over each P type well and N type well regions. The present LDD fabrication methods then provide a relatively consistent and easy method to fabricate CMOS LDD regions with N type and P type implants at a combination of different dosages and angles using first and second sidewall spacers, with less masking steps and improved device performance.