The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 08, 2000

Filed:

May. 19, 1998
Applicant:
Inventor:

Simon Gareth Ingram, Waterloo, CA;

Assignee:

Dalsa, Inc., , CA;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
257239 ; 257236 ; 257241 ;
Abstract

A bi-directional multi-tapped CCD sensor readout structure includes a well formed in a substrate, a channel formed in the well defining a channel direction, and a clocking structure disposed over the channel and oriented transversely to the channel direction. The clocking structure includes a plurality of register element sets. A first register element set includes a first floating sensing conductor and a plurality of clock signal conductors. The plurality of clock signal conductors includes a first clock signal conductor under which is defined a first junction at the electrical semiconductor junction between the well and the substrate and a second junction at the electrical semiconductor junction between the channel and the well. The first and second junctions define an inter-junction separation. The well is formed in the substrate and the channel is formed in the well so that a length of the inter-junction separation is controllable by a first clock signal applied to the first clock signal electrode. A clock signal source provides to the first clock signal conductor a first clock signal as either a clock high value, a clock low value and a reset value, the clock low value being a value between the clock high value and the reset value. The length of the inter-junction separation is zero when the first clock signal is the reset value.


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