The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 08, 2000

Filed:

May. 05, 1997
Applicant:
Inventor:

Yoshikazu Ohno, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
438253 ; 438238 ; 438239 ; 438254 ; 438256 ; 438229 ;
Abstract

A method of fabricating a semiconductor device is disclosed for connecting a bit line to a semiconductor substrate in a self-aligned fashion in non-contacting relation to a word line and precluding a crystal defect in the semiconductor substrate which might induce a leakage current. An isolation insulative film (2), gate oxide films (3), gate electrodes (4) (word lines), and insulative films (5) are formed on a semiconductor (e.g., Si) substrate (1) in sequential order, and sidewalls (6a to 6f) are formed while substrate protective oxide films (6g to 6i) are formed so that the semiconductor substrate (1) is not exposed. Source/drain regions (261 to 263) are formed, and an insulative film (7) made of Si.sub.3 N.sub.4, SiON and the like is deposited. Then, an interlayer insulative film (8) is formed over the top surface. The insulative film (7) has an etching rate lower than that of the interlayer insulative film (8).


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